The present invention relates to a technique for performing digital control of an output of a power supply.
There has been an accelerating trend in recent years toward digitalization in the field of power supply control, because the digitalization of a control circuit of a power supply enables a flexible, highly efficient control.
In a digitally-controlled power supply (hereinafter referred to as “digital control power supply”), an output (voltage or current) of the power supply is converted into a digital code by an A/D converter and is compared with a set target value. Then, a PWM control (PWM: Pulse Wide Modulation) is carried out according to the comparison result to thereby stabilize the output.
As a matter of course, the accuracy of the A/D conversion performed by the A/D converter affects the control accuracy of the digital control power supply.
Japanese Unexamined Patent Application Publication No. 07-131350 discloses a technique for improving the conversion accuracy of the A/D converter. The technique will be described with reference to FIG. 26.
FIG. 26 corresponds to FIG. 1 of Japanese Unexamined Patent Application Publication No. 07-131350. FIG. 26 shows an analog data conversion circuit to which the technique disclosed in Japanese Unexamined Patent Application Publication No. 07-131350 is applied. As shown in FIG. 26, the analog data conversion circuit includes an input terminal 1, an input amplifier 2, an A/D converter 3, a memory 4, a D/A converter 5, an output amplifier 6, an output terminal 7, a conversion control circuit 8, and an amplification control circuit 9. The amplification control circuit 9 includes a maximum value extraction unit 91, a minimum value extraction unit 92, a CPU 95, a D/A converter 96, and a D/A converter 97.
The input amplifier 2 amplifies an input analog signal which is input to the input terminal 1. The A/D converter 3 performs an A/D conversion to convert the input analog signal into an input digital signal. The input digital signal is stored in the memory 4. The input amplifier 2 is an amplifier having a variable amplification factor and connected to the D/A converter 96. The amplification factor of the input amplifier 2 changes with an analog voltage received from the D/A converter 96 as a control voltage.
The A/D converter 3 is an 8-bit A/D converter that compares a reference voltage (a reference top voltage RT and a reference bottom voltage RB) with the input analog signal and performs an A/D conversion. The A/D converter 3 is similar to the A/D converter of related art.
The digital signal stored in the memory 4 is subjected to desired digital processing by a circuit (not shown) and is then stored in the memory 4 again.
The amplification control circuit 9 reads out the input digital signal stored in the memory 4. Values in one cycle of the read input digital signal are compared with each other in the maximum value extraction unit 91, and a maximum value is extracted and given to the CPU 95. Similarly, values in one cycle are compared with each other in the minimum value extraction unit 92, and a minimum value is extracted and given to the CPU 95. Accordingly, the maximum value and the minimum value in one cycle are alternately given to the CPU 95.
The CPU 95 outputs data “n” to control an amplification factor α of the input amplifier 2 to be increased or decreased according to the given value of the maximum value or minimum value. Specifically, when the maximum value is smaller than “254” or when the minimum value is larger than “1”, the CPU 95 supplies, to the D/A converter 96, data to control the amplification factor α of the input amplifier 2 to be increased. When the maximum value is equal to “255” or when the minimum value is equal to “0”, the CPU 95 supplies, to the D/A converter 96, data to control the amplification factor α of the input amplifier 2 to be decreased. When the maximum value is equal to “254” or when the minimum value is equal to “1”, the CPU 95 does not change the data to be supplied to the D/A converter 96 so as to maintain the amplification factor α of the input amplifier 2, and causes the data “n” to be stored into the memory 4.
In summary, the analog data conversion circuit adjusts the amplification factor of the input amplifier 2 by estimating the range of the input analog signals from the input terminal 1 based on the maximum value and the minimum value in one cycle of the digital code obtained as a result of A/D conversion by the A/D converter 3. This enables the range of the signals input to the A/D converter 3 to constantly match the A/D convertible range of the A/D converter 3 (hereinafter referred to as “A/D conversion range”).